As semiconductor devices become more highly integrated, a channel width of a metal oxide semiconductor field effect transistor (MOSFET) may decrease such that the amount of driving current of the transistor is proportionately decreased. This decrease in driving current may lead to functional problems in the semiconductor device. For example, operation speed of the transistor may be reduced. Furthermore, a data-sensing margin of a semiconductor memory device using the different amount of driving current of the transistor, and the like may be degraded.
To address the problems discussed above, there has been proposed a fin transistor having a vertical channel, which may be capable of increasing the amount of driving current within a limited area. An example fin transistor will now be discussed with respect to FIGS. 1A through 1C.
FIG. 1A is a plan view of a conventional fin transistor and FIGS. 1B and 1C are cross-sections taken along lines A-A′ and B-B′ of FIG. 1, respectively. As illustrated in FIGS. 1A, 1B and 1C, a semiconductor fin 2 is provided on a semiconductor substrate 1. A device isolation pattern 3 is provided on the semiconductor substrate 1 such that it includes a lower portion of the semiconductor fin 2. A gate electrode 5 crosses over the semiconductor fin 2, wherein a gate oxide layer 4 is between the gate electrode 5 and the semiconductor fin 2. A doped region 6 is provided on the semiconductor fin 2 at either side of the gate electrode 5. The doped region 6 provides source/drain regions. The semiconductor fin 2 under the gate electrode 5 provides a channel region. The channel region has a three-dimensional structure, which protrudes perpendicularly over the semiconductor substrate 1. When a fin transistor is turned on, a plane channel is generated along an upper surface of the channel region, and vertical channels are formed along both side surfaces of the channel region.
Subsequently, an interlayer insulating layer 7 is provided on a surface of the semiconductor substrate 1, and the contact plug 9 fills an opening 8. Herein, the opening 8 is formed such that it penetrates the interlayer insulating layer 7 to expose at least a portion of the upper surface of the doped region 6. In other words, the contact plug 9 contacts the upper surface of the doped region 6.
Conventional fin transistors may have a wide channel region within a limited area provided by vertical channels formed along both side surfaces of the channel region. Accordingly, the amount of driving current of the fin transistor may be increased in comparison with that of a conventional planar transistor.
However, since the contact plug 9 contacts the upper surface of the doped region 6, resistance between a lower portion of the channel region (hereinafter referred to as a lower channel region) and the contact plug 9 may be greater than a resistance between an upper portion of the channel region (hereinafter referred to as an upper channel region) and the contact plug 9. In other words, a current path between the lower channel region and the contact plug 9 through the doped region 6 may be longer than a current path between the upper channel region and the contact plug 9 through the doped region 6. Generally, the doped region 6 has a higher resistivity than the contact plug 9. Therefore, the resistance between the lower channel region and the contact plug 9 may be greater than the resistance between the upper channel region and the contact plug 9. Accordingly, a voltage drop between the lower channel region and the contact plug 9 may be relatively large so that the amount of current flowing through the lower channel region becomes smaller than the amount of current flowing through the upper channel region. Thus, the fin transistor may not be able to secure the amount of driving current sufficiently in spite of the increased channel width.